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smps pf c tm irs2505lpbf 1 2015 - 9 - 2 boost pfc and smps control ic features ? critical - conduction mode pfc control (crcm) ? high pf and ultra - low thd ? wide line and load range ? regulated dc output voltage ? no secondary winding required ? cycle - by - cycle over - current protection ? output over - voltage protection ? ultra - low start - up current ? 20.8v internal zener clamp on vcc ? excellent esd and latch immunity ? rohs compliant ? 5 - pin sot - 23 package applications ? off - line power supply ? electronic ballast ? led power supply description the irs2505 l is a control ic for pfc boost converters operating in critical - conduct ion mode. the ic incorporates a voltage feedback loop for output voltage regulation combined with smart zero crossing detection to control the gate drive output without the need for a secondary inductor winding. dc output o ver - voltage protection and cycle - by - cycle over - current protection are also included . multi - functional inputs enable the irs2505l to perform all functions with only 5 pins. package options 5 lead sot23 base part number package type standard pack orderable part number form quantity irs2505lpbf 5l - sot - 23 tape and reel 3 000 IRS2505LTRPBF ordering information application diagram 1 3 5 4 irs 2505 l cmp pfc vbus vcc dc bus (+) 2 com dc bus ( - ) rect (+) rect ( - ) vcc ( - ) vcc (+)
irs2505lpbf 2 2015 - 9 - 2 qualification information ? qualification level industrial ?? (per jedec jesd 47e) comments: this family of ics has passed jedecs industrial qualification. irs consumer qualification level is granted by extension of the higher industrial level. moisture sensitivity level sot - 23 msl 1 ??? (per ipc/jedec j - std - 020c) esd machine model class b (per jedec standard eia/jesd22 - a115 - a) human body model class 2 (per eia/jedec standard jesd22 - a114 - b) ic latch - up test class i, level a (per jesd78a) rohs compliant yes ? qualification standards can be found at international rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales representative for further information. ??? higher msl ratings may be available for the specific package types li sted here. please contact your international rectifier sales representative for further information.
irs2505lpbf 3 2015 - 9 - 2 functional block diagram pfc cmp q s r 2 q r 1 q s r q vcc vcc com vbus 3 5 4 1 watchdog timer 2 ovp vbusov vbusreg ota vclamp ocp zx detect uvlo ct vcmpoh vcompon
irs2505lpbf 4 2015 - 9 - 2 timing diagram p f c i l p f c v d r a i n t t t v c c v p f c z x - v p f c o f f d c b u s o n - t i m e o f f - t i m e
irs2505lpbf 5 2015 - 9 - 2 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, all currents are defined positive into any pin. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units vpfc pfc pin voltage - 0.3 vcc + 0.3 v vbus vbus pin voltage - 0.3 vcc + 0.3 icc vcc pin supply current ? --- 25 ma icmp cmp pin current ?? --- 1 pd package power dissipation @ ta ? +25 oc sot - 23 5l --- 0.5 w r ja thermal resistance, junction to ambient sot - 23 5l --- 191 oc/w tj junction temperature - 55 150 oc ts storage temperature - 55 150 tl lead temperature (soldering, 10 seconds) --- 300 ? this ic contains a voltage clamp structure between the chip vcc and com which has a nominal breakdown voltage of 20.8v. this supply pin should not be driven by a dc, low impedance power source greater than the vclamp specified in the electrical characteristics section. ?? this ic contains a voltage clamp structure between the cmp and com which has a nominal breakdown voltage of 10.2v. this pin should not be driven by a dc, low impedance power source greater than the vzcmp specified in the electrical characteristics section.
irs2505lpbf 6 2015 - 9 - 2 recommended operating conditions for proper operation the device should be used within the recommended conditions. symbol definition min. max. units vcc supply voltage vccuv+ + 0.5v vclamp v icc supply current 0 10 ma vcmp cmp pin voltage 0 vzcmp v tj junction temperature - 40 125 oc recommended component values symbol component value units ccmp compensation capacitor value 0.68 f cvcc vcc filter capacitor 0.1 f cvbus vbus pin filter capacitor 1.0 nf
irs2505lpbf 7 2015 - 9 - 2 electrical characteristics vcc=14v, cvcc=0.1uf, ccmp=0.68uf, cpfc=1nf, cvbus=10nf, and ta= 25 c unless otherwise specified. symbol definition min typ max units test conditions supply characteristics vclamp vcc clamp voltage 19.8 20.8 21.8 v icc = 19 ma vccuv+ rising vcc under - voltage lock - out threshold 10.0 11.1 12.0 vccuv - falling vcc under - voltage lock - out threshold 7.0 7.9 9.0 vccuvhys vcc uvlo hysteresis 2.9 3.2 3.5 iqccuv micro - power start - up vcc supply current --- 46.0 6 0.0 a vcc = vccuv+ - 5 00mv rising iqcc no switching --- 1 .2 1.6 ma vcomp=0v, gbd icc50khz vcc current @ 50khz --- 1.6 2.0 ma pfc characteristics tonmax maximum pfc on - time 51 68 86 ? s vbusreg vbus pin regulation voltage 4.02 4.1 4.18 v vbusov+ vbus pin ovp threshold 4.30 4.50 4.70 vbusov - vbus pin ovp fault reset threshold 4.13 4.26 4.48 vbusoc+ vbus pin over - current threshold 0.45 0.5 3 0.62 vbus = 3v vpfczx + pfc pin zero - crossing arming threshold 0.39 0.4 0 0.51 vpfc rising , gbd vpfczx - pfc pin zero - crossing detection threshold 0.39 0.4 0 0.51 vpfc falling , gbd toffdly pfc pin off - time dela y --- 0.5 --- ? s tzxblnk pfc pin zero - crossing blank time --- 0.5 --- twd watch dog timer pulse interval 100 140 180 i cmp+ cmp pin ota io+ 25 3 3 40 ? a vbus=3.5v,vcmp=0v i cmp - cmp pin ota io - - 40 - 3 3 - 25 vbus=4.5v,vcmp=5v v cmpoh ota output voltage swing (high state) 9.9 10.2 11.5 v vbus=3.5v v cmpol ota output voltage swing (low state) --- 0 --- vbus=4.5v vcmpon minimum comp voltage for switching 1.21 1.50 1.83 vcmpflt ota output voltage in fault mode --- 0 --- vzcmp cmp pin clamp voltage 9.9 10.2 11.5 vbus=3.5v gbd : guaranteed by design
irs2505lpbf 8 2015 - 9 - 2 electrical characteristics vcc=14v, cvcc=0.1uf, ccmp=0.68uf, cpfc=1nf, cvbus=10nf, and ta= 25 c unless otherwise specified. gate driver output characteristics (pfc) vpfcon gate high voltage --- 13.0 --- v vpfcoffi gate low voltage during initial switch off period --- --- 0.1 vpfcoff gate low voltage (after initial switch off) 0.50 0.5 9 0.63 tpd gate initial switch off pull down time --- 500 --- ns tr output rise time --- 135 220 r ising, 10 % to 70% tf output fall time --- 20 3 5 falling, 80 % to 20% io+ output source current --- 50 --- ma io - output sink current --- 450 ---
irs2505lpbf 9 2015 - 9 - 2 pin assignments and definitions pin name description 1 cmp pfc error amplifier compensation 2 com ic power and signal ground 3 vcc logic and gate drive supply voltage 4 pfc pfc gate driver output and zero - crossing detection 5 vbus dc bus sensing input, ovp and ocp 1 3 5 4 i r s 2 5 0 5 c m p p f c v b u s v c c 2 c o m
irs2505lpbf 10 2015 - 9 - 2 functional description t he following topics are described in more detail below: 1) pfc control circuit 2) multi - function pfc pin 3) on - time modulation 4) over - voltage protection (ovp) 5) over - current protection (ocp) the irs2505l is primarily intended for but not limited to pre - regulator pfc boost converter front end stages in general power supplies and lighting applications such as led power supplies, fluorescent and hid ballasts. t he irs2505l may also be used in other converter topologies such as buck, buck - boost and flyba ck, where its small size and functionality can offer simplicity and cost advantage. it can also be used in converters where pfc is not required. 1. pfc control circuit the irs2505 is a high frequency smps pwm controller designed for boost pfc pre - regulators operat ing in critical - conduction mode (crcm), also known as transition (tm) or boundary mode (bm) . the pfc boost converter provides a regulated high voltage dc output over a range of ac line input voltage and load, while at the same time shaping the input current so that it follows the sinusoidal profile of the voltage resulting in high power factor and low total harmonic distortion (thd). figure 1 shows the main elements of the pfc boost converter ; t he input capacitor (cin) is for high frequency bypass and does not provide smoothing at low frequency under steady state operation . when a load is con n e cted at the output the rectified input voltage across cin is full wave rectified. during the on - time of the pfc mosfet (mpfc) , the irs2505 gate drive output (pfc) is high so the inductor (lpfc) current ramps up linearly to a peak current value . d uring the off - time the gate drive output is low and the inductor current linearly discharges back down to zero at which point mpfc is turned on again. the control loop response has to be slow compared to the line frequency so that the on time remains effectively constant over a single line half cycle ; except for some gradual increase as the voltage approaches the zero crossings, which improves thd. the off time varies during the ac line half cycle being longest at the peak. figure 1: boost - type converter and inductor current during critical - conduction mode. the result is a triangular shaped inductor current that varies in frequency depend ing on the level of the instantan eous rectified ac line voltage shown in f igure 2. the maximum switching frequency occurs at the zero - crossings of the rectified ac line voltage and the minimum at the peak of the rectified ac line voltage. the average induc tor current is equal to half of the peak, which is equal to the instantaneous line input current after the high frequency elements have been filtered out. c i n c b u s l p f c m p f c d p f c ( + ) ( - ) ( - ) ( + ) r e c t i f i e d a c l i n e i n p u t d c b u s i l p f c t o n - t i m e o f f - t i m e
irs2505lpbf 11 2015 - 9 - 2 figure 2: pfc inductor current during the rectified ac line voltage cycle. the irs2505 internal control circuit blocks shown in figure 3 include ; the feedback error amplifier controlling on - time via timing capacitor (ct), zero - crossing (zx) detection and off - time control, gate drive output, over - voltage protection (ovp) and over - current protection (ocp) . the pfc pin is a multi - function input/output pin used for driving the external pfc mosfet gate and also for sensing the pfc inductor current zero - crossing during the off - time . the vbus pin is also a multi - function pin use d for monitoring the dc bus voltage through an external divider network and also measuring the mosfet (mpfc) source current. an internal ota compares the voltage feedback with an accurate internal voltage reference (vbusreg) to control the cmp pin voltage by charging and discharging the external compensation capacitor (ccmp). the voltage level at the cmp pin determines the on - time to control power transfer to the output. the mosfet current is measured with a current - sensing resistor and then ac - coupled onto the vbus pin through an external series resistor and capacitor. figure 3: pfc control circuitry v , i time ac line voltage ac line current inductor current cross - over distortion o f f t i m e p f c l o g i c o c p o v p 4 o n t i m e 1 5 4 . 1 v u v l o 3 2 v b u s c m p v c c c o m p f c c t v b u s ( + ) v b u s ( - ) r e c t ( + ) r e c t ( - ) 9 . . . 1 9 . 8 v ( + ) ( - ) +
irs2505lpbf 12 2015 - 9 - 2 2. pfc multi - function pin the multi - function pfc pin performs the following two functions: 1) pfc gate drive output. 2) pfc inductor current zero - crossing detection. during each switching cycle illustrated in f igure 4, at the beginning of each cycle the pfc pin gate drive output pulls the pfc pin voltage high to approximately vcc - 1v and the external pfc mosfet turns on ; the on - time duration is set by t he cmp pin voltage. t he internal pfc control loop steers the cmp pin voltage to control the on - time such that if the dc bus voltage increases then the cmp pin voltage and on - time will decrease. this will decrease the peak inductor curre nt each switching cycle transferring less energy and causing the d c bus voltage to decrease. if the dc bus voltage decreases, then the cmp pin voltage and on - time will increase having the opposite effect. this negative feedback control regulates the dc bus to a constant voltage over ac line voltage or output load vari ations . the speed of the control loop is determined by the internal ota trans - conductance and compensation capacitor ccmp. at the end of each on time period, the pfc pin gate drive circuit pull s the pfc pin to com and the external pfc mosfet turns off. after a short initial switch off delay (t pd ), the internal gate drive pull - down turns off and the pfc pin is then weakly pulled up and clamped at approximately one diode forward voltage drop (vpfc off), which is well below the gate threshold of the mosfet (mpfc) ensuring that it will not begin to switch on. during the off - time the pfc inductor current discharges through the boost diode into the dc output capacitor and load. when the inductor current falls to zero, the drain voltage falls from the level of the output voltage plus the output diode forward voltage and transitions negatively. during this transition current flows through the mosfet parasitic gate to drain capacitance c gd overcoming the in ternal weak pull up and causing the gate voltage to drop below the threshold v pfczx - . after remaining below this threshold for a period of t zxblank , the pfc gate drive will be turned on again to start the next switching cycle and so the sequence repeats. t o ensure zx detection , a minimum voltage headroom is needed between the peak line voltage at high line and the output voltage. this value depends on the mosfet c gd , a value of 60 - 70v is typical . t o ope r ate with a smaller headroom 5 00v minimum rated capacitor around 100pf may be added between drain and source. figure 4: pfc timing diagram. p f c i l p f c v d r a i n t t t v c c v p f c z x - v p f c o f f d c b u s o n - t i m e o f f - t i m e
irs2505lpbf 13 2015 - 9 - 2 3. pfc on - time modulation f ixed on - time over the entire half cycle of the line input voltage produces a peak inductor current that naturally follows the sinusoidal shape of the l ine input voltage. the filtered, averaged line input current is in phase with the line input voltage to provide high power factor . h owever some harmonic distortion of the current is still present mostly due to cross - over distortion occurring near the zero - crossings of the line input voltage as shown in figure 2 . to achieve very low harmonics within the limits of international standard s and to meet general market requirements, an additional on - time modulation function is included in the irs2505l , which dynamically increases the on - time as the line input voltage nea rs the zero - crossings . as illustrated in figure 5, t he peak lpfc current and therefore the smoothed line input current increase slightly higher near the zero - crossings of the line input voltage. this reduces the amo unt of cross - over distortion in the line input current and improves the shape of the current r educ ing the thd and harmonics to low levels. figure 5: pfc on - time modulation. 4. dc bus over - voltage protection (ovp) the vbus pin includes output over - voltage protection (ovp). should the vbus pin feedback voltage exceed the internal over - voltage protection threshold (vbusov+) then the pfc gate drive will turn off until the vbus pin voltage again f alls below the over - voltage restart threshold (vbusov - ) to resume normal operation. ilpfc pfc pin near peak region of rectified ac line near zero - crossing region of rectified ac line
irs2505lpbf 14 2015 - 9 - 2 5. over - current protection (ocp) as well as sensing the output voltage feedback, t he vbus input also includes a cycle - by - cycle , ac - coupled, over - current protection (ocp) function. the external network required to combine these two inputs is shown in figure 6 . the high - frequency ramp shaped voltage produced across the current - sensing resistor (rcs) is coupled onto the vbus feedback with an exte rnal series resistor (r1) and capacitor (c1) as shown in figure 7 . an internal over - current protection circuit detects the difference between the peak and average of the combined signal so that if the triangular - shaped voltage peak at the vbus input exceed s vbusreg by vbusoc+ the gate drive is immediately driven low . the capacitor cvbus is added to make the current sense signal more triangular so that its peak value will be close to half its average. the ocp function will safely limit the peak current in e ach switching cycle to prevent mosfet damage during low ac line conditions , overload or during fast mains voltage interrupts. it should be remembered that in any boost converter it is not possible to incorporate full output current control or short circuit protection by controlling the switching of mpfc. shorting the output should be avoided as it will short the input and blow a fuse! figure 6: ac - coupled over - current protection circuit. figure 7: ocp circuit timing diagram. vbus rcs r 1 c 1 dc bus voltage rbus 1 rbus 2 vcs mpfc boost switching node 5 2 com cvbus v c s t t v b u s d c o f f s e t ( f r o m d c b u s m e a s u r e m e n t ) t p f c v b u s o c + n o r m a l m o d e o c p m o d e
irs2505lpbf 15 2015 - 9 - 2 package details: 5 lead sot23
irs2505lpbf 16 2015 - 9 - 2 tape and reel details: 5 lead sot23
irs2505lpbf 17 2015 - 9 - 2 tape and reel details: 5 lead sot23
irs2505lpbf 18 2015 - 9 - 2 part marking information: 5 lead sot23 top marking bottom marking y w l c l o t c o d e d a t e c o d e b i r l o g o p a r t n o .
irs2505lpbf 19 2015 - 9 - 2 revision history major changes since the last revision date description of change june 2 0 , 201 3 first release september 2, 2015 updated block diagram and functional description. added test limits for multiple parameters. published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2015 all rights reserved. important notice the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (beschaffenheitsgarantie ). with respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product , infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limita tion warranties of non - infringement of intellectual property rights of any third party. in addition , any information given in this document is subject to customer s compliance with its obligations stated in this document and any applicable legal requirem ents, norms and standards concerning customers products and any use of the product of infineon technologies in customers applications. the data contained in this document is exclusively intended for technically trained staff. it is the responsibility o f customers technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. for further information on the product, t echnology, delivery terms and conditions and prices please contact your nearest infineon technologies o ffice ( www.infineon.com ). warnings due to technical requirements products may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies o ffice. except as otherwise explicitly approved by infineon technologies in a written document signed by authorized representatives of infineon technologies, infineon technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.

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